1. Field of the Invention
This invention relates generally to telecommunications, and, more particularly, to providing a multiple time-constant circuit for performing electrostatic discharge clamping.
2. Description of the Related Art
In communication systems, particularly telephony such as a Plain Old Telephone System (POTS), it is common practice to transmit signals between a subscriber station and a central switching office via a two-wire, bi-directional communication channel. A line card generally connects the subscriber station to the central switching office. The functions of the line card include supplying talk battery, performing wake-up sequences of circuits to allow communications to take place, and the like. Voltage signals are processed and conditioned when being driven onto telecommunication lines. These communication systems employ various electronic devices. Today's state of the art electronics provide for various circuits that may be implemented onto a single integrated circuit chip. Often, many electronic components are generally placed on an integrated circuit device. As technology improves in the area of processing of semiconductor devices, more electronic functions and devices are implemented onto integrated circuit chips.
One problem associated with handling and operating electronic devices, such as integrated circuit chips, includes protecting the devices from electrostatic discharge (ESD). Electrostatic discharges may cause various problems on electronic devices. For example, a large electrostatic may cause a sufficient energy spike in various circuitry of the electronic device such that damage to certain portions of the device may occur. In order to reduce the possibility of damage in electronic devices due to electrostatic discharges, designers have implemented various ESD protection circuitries in electronic devices. One such circuit is illustrated in FIG. 1.
Turning now to FIG. 1, a prior art ESD clamping circuit 100 is illustrated. The ESD clamping circuit 100 of FIG. 1 generally comprises a clamping device 110, an inverter circuit 120, and a charging circuit 130. The charging circuit 130 may comprise a high resistance pull-up 140 and a capacitance circuit 160. Field-effect transistors, such as MOSFETs may be employed in the clamping device 110, the inverter circuit 120 and the charging circuit 130. Upon an occurrence of an ESD event, a Vdd signal 150 (positive voltage supply) may experience a rapid and large rise in voltage. Initially, when the Vdd signal 150 experiences a positive-voltage event, such that its voltage rises rapidly, a first node 155 in the charging circuit 130 generally remains at a potential of SVss 170 (substrate ground voltage-level) and also at the same potential relative to a potential of Vss 180 (the ground voltage-level). This is true because of the gate capacitance of various MOSFETs in the charging circuit 130.
During the positive-voltage event, the Vdd signal 150 will start to climb and then the inverter circuit 120 becomes active once the Vdd signal 150 rises above a threshold voltage of the inverter circuit 120. The first node 155 will then be held at the Vss potential signal 180, which will cause the voltage level of a second node 125 to begin to climb. The second node 125 will climb up to the level of the Vdd signal 150, which is at this point beyond the threshold voltage, thereby activating the clamping device 110. The clamping device 110 clamps the voltage experienced by the clamping circuit 100.
The activation of the clamping device 110 occurs when the Vdd signal 150 has a relatively fast rise time. At this point, the clamping device 110 will be activated and minimize further increases in the Vdd signal 150. Generally, a small amount of current will flow through the high resistance pull-up circuit 140, which may be a weak P-channel device. Therefore, that small current will require a substantial amount of time to charge up the first node 155. When the first node 155 becomes charged up to the threshold of the inverter circuit 120, the inverter circuit 120 becomes deactivated, which prompts the second node 125 to transition. This causes the deactivation of the clamping device 110, thereby turning off the clamping function of the circuit 100.
One problem associated with the implementation shown in FIG. 1 is that the clamping function may be inadvertently triggered by a normal power-on event that has a fast rise time but does not exceed normal operation voltages. Among the problems associated with triggering an ESD clamp upon a power up sequence includes interferences with power-on sequences, a possible reduction in the reliability of the ESD clamps, and/or occurrence of unintended device behavior, such as device latch-up due to large clamp currents. Another problem associated with the implementation shown in FIG. 1 is that the deactivation of the clamping function may occur (i.e., turning the clamping circuit 100 clamping function off) before a desirable time because the ESD event may not be completely extinguished before the clamping function is deactivated. Therefore, the electronic device hosting the circuit 100 may become damaged.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.